1. Field of the Invention
The invention relates to the field of complementary metal-oxide-semiconductor (CMOS) processing.
2. Prior Art
Integrated circuits employing CMOS transistors have become more widely used in recent years. These circuits are known to have a number of advantages over p-channel or n-channel circuits, such as higher noise immunity, lower power consumption and much higher resistance to "soft" failures associated with ionizing radiation.
Typically, in the fabrication of CMOS transistors two separate doping steps are used to form the source and drain regions for the n-channel transistors and the p-channel transistors. The doping levels for these regions is typically higher than the doping levels associated with other processing steps, such as ion implantation steps used to adjust threshold voltages, thus necessitating separate source/drain doping steps.
In some processes, two separate masking steps are used to dope the source/drain regions of the complementary transistors. For example, first the selected regions for the source/drain regions of the n-channel transistors are covered and a p-type dopant is implanted to form the p-channel transistors. Then, the p-channel transistors are covered with, for example, a photoresist and an n-type dopant is used to form the n-channel transistors. Obviously, this process requires two separate masking steps to form the complementary source/drain regions.
In another process, only a single masking step is used. First, by way of example, the selected regions for the source/drain regions of the n-channel transistors are covered with a photoresist and a p-type dopant is used to form the p-channel transistors. The doping level for these p-type source/drain regions is made higher than is required. Then, the photoresist is removed and the substrate is subjected to an n-type dopant. The n-type dopant forms the source/drain regions of the n-type transistors and also dopes the source/drain regions of the p-channel transistors. However, since extra dopant was used for the p-channel transistors, the counter doping from the n-type dopant does not change the conductivity type of the source/drain regions for the p-channel transistors. Thus, the complementary transistors are formed with only a single masking step. One problem with this process is that it is difficult to control the doping level in the counter doped source/drain regions.
As will be seen, the present invention permits complementary source/drain regions to be formed with a single masking step and without the counter doping. It permits the doping levels of the complementary source/drain regions to be accurately controlled. The present invention makes use of the known phenomena, specifically that oxides grow more quickly on more highly doped silicon. The invented process also permits the forming of complementary doped gates for the CMOS transistors.